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M30LW128D
128 Mbit (two 64Mbit, x8/x16, Uniform Block, Flash Memories) 3V Supply, Multiple Memory Product
PRELIMINARY DATA
FEATURES SUMMARY s TWO M58LW064D 64Mbit FLASH MEMORIES STACKED IN A SINGLE PACKAGE
s
Figure 1. Packages
WIDE x8 or x16 DATA BUS for HIGH BANDWIDTH SUPPLY VOLTAGE - VDD = 2.7 to 3.6V for Program, Erase and Read operations
s
s
- VDDQ = 1.8 to VDD for I/O buffers ACCESS TIME - Random Read 110ns - Page Mode Read 110/25ns
TSOP56 (N) 14 x 20 mm
s
PROGRAMMING TIME - 16 Word Write Buffer - 16s Word effective programming time
TBGA
s
128 UNIFORM 64 KWord/128KByte MEMORY BLOCKS BLOCK PROTECTION/ UNPROTECTION PROGRAM and ERASE SUSPEND 128 bit PROTECTION REGISTER COMMON FLASH INTERFACE 100, 000 PROGRAM/ERASE CYCLES per BLOCK ELECTRONIC SIGNATURE - Manufacturer Code: 20h - Device Code M30LW128D: 8817h
TBGA64 (ZA) 10 x 13mm
s s s s s
FBGA
s
LFBGA88 (ZE) 8 x 10mm
February 2003
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3. TSOP56 Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 4. TBGA64 Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 5. LFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 7 8 9
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Address Input (A0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Address Inputs (A1-A22). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Address Input (A23). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Data Inputs/Outputs (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Reset/Power-Down (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Byte/Word Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Status/(Ready/Busy) (STS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Program/Erase Enable (VPEN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VDD Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VDDQ Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VSSQ Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 MEMORY ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 2. Single M58LW064D Device Enable, E2, E1 and E0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3. M30LW128D Device Enable, A23 and E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 6. Stacked Flash Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 7. Block Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 13 14
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Page Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Automatic Low Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 4. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Read Memory Array Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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Read Query Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Read Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Clear Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Word/Byte Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Write to Buffer and Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Block Protect Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Blocks Unprotect Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Configure STS Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 5. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 6. Configuration Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 7. Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 8. Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 8. Word-Wide Read Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 9. Byte-Wide Read Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 10. Program/Erase Times and Program/Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 24 STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Program Status (Bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 VPEN Status (Bit 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Block Protection Status (Bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 11. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 12. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 13. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 9. AC Measurement Input Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 10. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 14. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 15. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11. Bus Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 16. Bus Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 12. Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 17. Page Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 13. Write AC Waveform, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 18. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 29 29 29 30 31 31 32 32 33 33
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Figure 14. Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 19. Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 15. Reset, Power-Down and Power-Up AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 20. Reset, Power-Down and Power-Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 34 34 35 35
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 16. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Outline . . . . . . . Table 21. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Mechanical Data Figure 17. TBGA64 - 10x13mm, 8 x 8 ball array 1mm pitch, Package Outline . . . . . . . . . . . . . . . Table 22. TBGA64 - 10x13mm, 8 x 8 ball array, 1 mm pitch, Package Mechanical Data . . . . . . . Figure 18. LFBGA88 8x10 mm - 8x10 ball array, 0.8mm pitch, Bottom View Package Outline Table 23. LFBGA88 8x10mm - 8x10 ball array, 0.8mm pitch, Package Mechanical Data . . . . . . 36 36 37 37 38 38
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 24. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 APPENDIX A. BLOCK ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 25. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 APPENDIX B. COMMON FLASH INTERFACE - CFI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 26. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 27. CFI - Query Address and Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 28. CFI - Device Voltage and Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 29. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 30. Block Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 31. Extended Query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 42 43 44 44 45
APPENDIX C. FLOW CHARTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 19. Write to Buffer and Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . Figure 20. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . Figure 21. Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 22. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . Figure 23. Block Protect Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 24. Blocks Unprotect Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 25. Protection Register Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . Figure 26. Command Interface and Program Erase Controller Flowchart (a) . . . . . . . . . . . . . . . . Figure 27. Command Interface and Program Erase Controller Flowchart (b) . . . . . . . . . . . . . . . . Figure 28. Command Interface and Program Erase Controller Flowchart (c). . . . . . . . . . . . . . . . 46 47 48 49 50 51 52 53 54 55
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 32. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
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SUMMARY DESCRIPTION The M30LW128D is a 128 Mbit device that is composed of two separate 64 Mbit M58LW064D Flash memories. The device can be erased electrically at block level and programmed in-system using a 2.7V to 3.6V (V DD) supply for the circuitry and a 1.8V to V DD (VDDQ) supply for the Input/Output pins. The bus width can be configured for x8 or x16 for the devices available in the TSOP56 (14 x 20 mm) and TBGA64 (10x13mm, 1mm pitch) packages. The bus width is set to x16 for the devices available in the LFBGA88 (8x10mm, 0.8mm pitch) package. Each internal M58LW064D has 3 Chip Enable signals to allow up to 4 memories to be connected together without the use of additional glue logic. In this way the address space is contiguous and the microprocessor only requires one Chip Enable, E, to control both memories. The device is divided into 128 blocks of 1Mbit (2 x 64 x 1Mb) that can be erased independently so it is possible to preserve valid data while old data is erased. Program and Erase commands are written to the Command Interface of the device. An onchip Program/Erase Controller (P/E.C) simplifies the process of programming or erasing the device by taking care of all of the special operations that are required to update the memory contents. The end of a Program or Erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the device is consistent with JEDEC standards. The Write Buffer allows the microprocessor to program from 1 to 16 Words in parallel, both speeding up the programming and freeing up the microprocessor to perform other work. A Word Program command is available to program a single word.
Erase can be suspended in order to perform either Read or Program in any other block and then resumed. Program can be suspended to Read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles. Individual block protection against Program or Erase is provided for data security. All blocks are protected during power-up. The protection of the blocks is non-volatile; after power-up the protection status of each block is restored to the state when power was last removed. Software commands are provided to allow protection of some or all of the blocks and to cancel all block protection bits simultaneously. All Program or Erase operations are blocked when the Program Erase Enable input VPEN is low. The Reset/Power-Down pin is used to apply a Hardware Reset to the enabled memory and to set the device in power-down mode. The STS signal is an open drain output that can be used to identify the Program/Erase Controller status. It can be configured in two modes: Ready/ Busy mode where a static signal indicates the status of the P/E.C, and Status mode where a pulsing signal indicates the end of a Program or Block Erase operation. In both modes it can be used as a system interrupt signal, useful for saving CPU time. The STS signal is only available with the TSOP56 and TBGA64 packages. Each memory includes a 128 bit Protection Register. The Protection Register is divided into two 64 bit segments, the first one is written by the manufacturer (contact STMicroelectronics to define the code to be written here), while the second one is programmable by the user. The user programmable segment can be locked.
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Figure 2. Logic Diagram
VDD VDDQ
Table 1. Signal Names
A0 (1) A1-A22 A23 Address input (used in X8 mode only) Address inputs Address Input to select memory Byte/Word Organization Select Data Inputs/Outputs Chip Enable Output Enable Reset/Power-Down Status/(Ready/Busy) Program/Erase Enable Write Enable Supply Voltage Input/Output Supply Voltage Ground Input/Output Ground Not Connected Internally Do Not Use
24 A0(1)-A23 VPEN BYTE(1) W E G RP M30LW128D
BYTE (1) DQ0-DQ15 E
16 DQ0-DQ15 STS(1)
G RP STS (1) VPEN W VDD VDDQ VSS VSSQ NC
VSS VSSQ
AI07504
DU
Note: 1. Not available with LFBGA88 package.
Note: 1. Not available with LFBGA88 package.
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Figure 3. TSOP56 Connections
A22 NC A21 A20 A19 A18 A17 A16 VDD A15 A14 A13 A12 E VPEN RP A11 A10 A9 A8 VSS A7 A6 A5 A4 A3 A2 A1
1
56
NC W G STS DQ15 DQ7 DQ14 DQ6 VSS DQ13 DQ5 DQ12 DQ4 VDDQ VSSQ DQ11 DQ3 DQ10 DQ2 VDD DQ9 DQ1 DQ8 DQ0 A0 BYTE A23 NC
AI07508
14 43 M30LW128D 15 42
28
29
Note: Pin 2 (E1 for a single M58LW064D device) and pin 29 (E2 for a single M58LW064D device) are NC (not connected). They should be tied to ground (VSS) to assure compatibility with a single chip 128Mbit device.
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M30LW128D
Figure 4. TBGA64 Connections (Top view through package)
1
2
3
4
5
6
7
8
A
A1
A6
A8
VPEN
A13
VDD
A18
A22
B
A2
VSS
A9
E
A14
DU
A19
NC
C
A3
A7
A10
A12
A15
DU
A20
A21
D
A4
A5
A11
RP
DU
DU
A16
A17
E
DQ8
DQ1
DQ9
DQ3
DQ4
DU
DQ15
STS
F
BYTE
DQ0
DQ10
DQ11
DQ12
DU
DU
G
G
A23
A0
DQ2
VDDQ
DQ5
DQ6
DQ14
W
H
NC
DU
VDD
VSSQ
DQ13
VSS
DQ7
NC
AI07505
Note: Ball B8 (E1 for a single M58LW064D device) and ball H1(E2 for a single M58LW064D device) are NC (not connected). They should be tied to ground (VSS ) to assure compatibility with a single chip 128Mbit device.
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M30LW128D
Figure 5. LFBGA Connections (Top view through package)
1
2
3
4
5
6
7
8
A
DU
DU
DU
DU
B
A4
A18
A19
NC
VDD
NC
A21
A11
C
A5
NC
NC
VSS
NC
NC
A22
A12
D
A3
A17
NC
VPEN
NC
NC
A9
A13
E
A2
A7
NC
NC
NC
A20
A10
A15
F
A1
A6
NC
RP
W
A8
A14
A16
G
A0
DQ8
DQ2
DQ10
DQ5
DQ13
NC
NC
H
NC
DQ0
DQ1
DQ3
DQ12
DQ14
DQ7
NC
J
NC
G
DQ9
DQ11
DQ4
DQ6
DQ15
VDDQ
K
E
VDD
DU
NC
NC
NC
VDDQ
NC
L
NC
VSSQ
VDDQ
VDD
NC
VSSQ
VSS
NC
M
DU
DU
DU
DU
AI07555
Note: 1. The BYTE, STS and A0 connections are not available with the LFBGA88 package.
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M30LW128D
SIGNAL DESCRIPTIONS See Figure 2, Logic Diagram and Table 1, Signal Names, for a brief overview of the signals connected to this device. Address Input (A0). The A0 address input is used to select the higher or lower Byte in x8 mode. It is not used in x16 mode (where A1 is the Lowest Significant bit). The A0 address input is not available with the LFBGA88 package. Address Inputs (A1-A22). The Address Inputs are used to select the cells to access in the memory array during Bus Read operations either to read or to program data to. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. The device must be enabled (refer to Table 3, M30LW128D Device Enable) when selecting the addresses. The address inputs are latched on the rising edge of Write Enable or Chip Enable, E, whichever occurs first. Address Input (A23). Address Input A23 is used to select between the two internal memories. When it is High, VIH, it selects the Upper Memory, when it is Low, V IL, it selects the Lower Memory. Refer to Memory Enable section for more details. Data Inputs/Outputs (DQ0-DQ15). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation, or are used to input the data during a program operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine. When used to input data or Write commands they are latched on the rising edge of Write Enable or Chip Enable, E, whichever occurs first. When the device is enabled and Output Enable is low, V IL, the data bus outputs data from the memory array, the Electronic Signature, the Block Protection status, the CFI Information or the contents of the Status Register. The data bus is high impedance when the device is deselected, Output Enable is high, VIH, or the Reset/Power-Down signal is low, VIL. When the Program/Erase Controller is active the Ready/Busy status is given on DQ7. Chip Enable (E). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. The M30LW128D stacked memory uses the A23 address line and the external Chip Enable, E, to select and enable the internal memories. Refer to Memory Enable section and Table 3, for more details. When the Chip Enable deselects the memory, power consumption is reduced to the Standby level, IDD1.
Output Enable (G). The Output Enable, G, gates the outputs through the data output buffers during a read operation. When Output Enable, G, is at VIH the outputs are high impedance. Write Enable (W). The Write Enable input, W, controls writing to the Command Interface, Input Address and Data latches. Both addresses and data can be latched on the rising edge of Write Enable. Reset/PowerReset/Power-Down (RP). The Down signal can be used to apply a Hardware Reset to the memory. A Hardware Reset is achieved by holding Reset/ Power-Down Low, VIL, for at least tPLPH. When Reset/Power-Down is Low, VIL, the Status Register information is cleared and the power consumption is reduced to power-down level. The device is deselected and outputs are high impedance. If Reset/Power-Down goes low, V IL,during a Block Erase, a Write to Buffer and Program or a Block Protect/Unprotect the operation is aborted and the data may be corrupted. In this case the STS pin stays low, V IL, for a maximum timing of tPLPH + tPHBH, until the completion of the Reset/Power-Down pulse. After Reset/Power-Down goes High, V IH, the device will be ready for Bus Read and Bus Write operations after tPHQV. Note that STS does not fall during a reset, see Ready/Busy Output section. In an application, it is recommended to associate Reset/Power-Down pin, RP, with the reset signal of the microprocessor. Otherwise, if a reset operation occurs while the device is performing an Erase or Program operation, the device may output the Status Register information instead of being initialized to the default Asynchronous Random Read. Byte/Word Organization Select (BYTE). The Byte/Word Organization Select signal is used to switch between the x8 and x16 bus widths of the memory. When Byte/Word Organization Select is Low, VIL, the memory is in x8 mode, when it is High, V IH, the memory is in x16 mode. The Byte/Word Organization Select signal is not available with the LFBGA88 package. Status/(Ready/Busy) (STS). The STS signal is an open drain output that can be used to identify the Program/Erase Controller status. It can be configured in two modes: s Ready/Busy - the pin is Low, VOL, during Program and Erase operations and high impedance when the memory is ready for any Read, Program or Erase operation.
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M30LW128D
s
Status - the pin gives a pulsing signal to indicate the end of a Program or Block Erase operation.
After power-up or reset the STS pin is configured in Ready/Busy mode. The pin can be configured for Status mode using the Configure STS command. When the Program/Erase Controller is idle, or suspended, STS can float High through a pull-up resistor. The use of an open-drain output allows the STS pins from several devices to be connected to a single pull-up resistor (a Low will indicate that one, or more, of the memories is busy). STS is not Low during a reset unless the reset was applied when the Program/Erase controller was active. The STS signal is not available with the LFBGA88 package. Program/Erase Enable (VPEN). The Program/ Erase Enable input, VPEN, is used to protect all blocks, preventing Program and Erase operations from affecting their data. Program/Erase Enable must be kept High during all Program/Erase Controller operations, other-
wise the operations is not guaranteed to succeed and data may become corrupt. VDD Supply Voltage. VDD provides the power supply to the internal core of the device. It is the main power supply for all operations (Read, Program and Erase). VDDQ Supply Voltage. VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered independently from VDD. VDDQ can be tied to VDD or can use a separate supply. It is recommended to power-up and power-down VDD and VDDQ together to avoid any condition that would result in data corruption. VSS Ground. Ground, VSS, is the reference for the core power supply. It must be connected to the system ground. VSSQ Ground. VSSQ ground is the reference for the input/output circuitry driven by V DDQ. VSSQ must be connected to V SS. Note: Each device in a system should have VDD and VDDQ decoupled with a 0.1F ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 10, AC Measurement Load Circuit.
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M30LW128D
MEMORY ENABLE Each internal M58LW064D memory has 3 Chip Enable signals to allow up to 4 memories to be connected together without the use of additional glue logic, see Table 2, Single M58LW064D Device Enable. In this way the address space is contiguous and the microcontroller only requires one Chip Enable, E, to control both memories. Figure 6 shows how a 128Mbit Stacked Flash memory is created using two M58LW064D memories. One of the memories is located in the Upper Address space and is referred to as the Upper Memory, the other is located in the lower address space and is referred to as the Lower Memory, see Figure 7, Block Addresses. The E0, E1 and E2 Chip Enables of each M58LW064D memory are connected internally, as shown in Figure 6.
The external signal A23 is used to select between the Upper and Lower memories. A23 is connected to E2 of the Upper Memory and to E1 of the Lower Memory. E1 of the Upper Memory is always connected to VDD while E2 of the Lower Memory is always connected to VSS. The external Chip Enable, E, is used to enable or disable the memory selected by A23, see Table 3, M30LW128D Device Enable. E is connected to the E0 signal of both memories. The M30LW128D (TSOP56 and TBGA64 packages only) supports both x8 and x16 bus widths. It is also possible to have a x32 bus width by connecting two x16 bus width M30LW128D devices together. Note that the two M30LW128D devices must use the same E0 as Chip Enable, as E1 and E2 are not connected internally.
Table 2. Single M58LW064D Device Enable, E2, E1 and E0
E2 VIL VIL VIL VIL VIH VIH VIH VIH E1 VIL VIL VIH VIH VIL VIL VIH VIH E0 VIL VIH VIL VIH VIL VIH VIL VIH Device Enabled Disabled Disabled Disabled Enabled Enabled Enabled Disabled
Table 3. M30LW128D Device Enable, A23 and E
A23 E2UM = E1LM (1) VIL VIL VIH VIH
Note: 1. UM = Upper Memory, LM = Lower Memory.
Internal Signals E1UM (1) E2LM (1)
Chip Enable, E E0UM = E0LM (1) VIL Upper Memory Disabled Disabled Enabled Disabled Lower Memory Enabled Disabled Disabled Disabled
VDD (VIH)
VSS (VIL)
VIH VIL VIH
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M30LW128D
Figure 6. Stacked Flash Memory
VDD
E1 E2 E0 64 Mbit Upper Memory
A0-A22
DQ0-DQ15
64 Mbit Lower Memory E A23 E0 E1 E2
VSS
PACKAGE
AI07506
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M30LW128D
Figure 7. Block Addresses
Byte (x8) Bus Width FFFFFFh FE0000h FDFFFFh FC0000h UPPER MEMORY Total of 64 1 Mbit Blocks 83FFFFh 820000h 81FFFFh 800000h 7FFFFFh 7E0000h 7DFFFFh 7C0000h LOWER MEMORY Total of 64 1 Mbit Blocks 03FFFFh 020000h 01FFFFh 000000h 1 Mbit or 128 KBytes 1 Mbit or 128 KBytes 01FFFFh 010000h 00FFFFh 000000h 1 Mbit or 128 KBytes 1 Mbit or 128 KBytes 1 Mbit or 128 KBytes 1 Mbit or 128 KBytes 41FFFFh 410000h 40FFFFh 400000h 3FFFFFh 3F0000h 3EFFFFh 3E0000h 7FFFFFh 7F0000h 7EFFFFh 7E0000h
Word (x16) Bus Width
1 Mbit or 128 KBytes 1 Mbit or 128 KBytes
1 Mbit or 64 KWords 1 Mbit or 64 KWords
1 Mbit or 64 KWords 1 Mbit or 64 KWords 1 Mbit or 64 KWords 1 Mbit or 64 KWords
1 Mbit or 64 KWords 1 Mbit or 64 KWords
AI07507
Note: Also see Appendix A, Table 25 for a full listing of the Block Addresses
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M30LW128D
BUS OPERATIONS There are 6 bus operations that control each memory. Each of these is described in this section, see Tables 4, Bus Operations, for a summary. On Power-up or after a Hardware Reset the device defaults to Read Array mode (Page Read). Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the device and do not affect bus operations. Bus Read. Bus Read operations read from the memory cells, or specific registers (Electronic Signature, Status Register, CFI and Block Protection Status) in the Command Interface. A valid bus operation involves setting the desired address on the Address inputs, enabling the device (refer to Table 3), applying a Low signal, VIL, to Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 11, Bus Read AC Waveforms, and Table 16, Bus Read AC Characteristics, for details of when the output becomes valid. Page Read. Page Read operations are used to read from several addresses within the same memory page. Each memory page is a 4 Words or 8 Bytes and has the same A3-A22. In x8 mode only A0, A1 and A2 may change, in x16 mode only A1 and A2 may change. Valid bus operations are the same as Bus Read operations but with different timings. The first read operation within the page has identical timings, subsequent reads within the same page have much shorter access times. If the page changes then the normal, longer timings apply again. See Figure 12, Page Read AC Waveforms and Table 17, Page Read AC Characteristics for details on when the outputs become valid. Bus Write. Bus Write operations write to the Command Interface in order to send commands to the device or to latch addresses and input data to program.
A valid Asynchronous Bus Write operation begins by setting the desired address on the Address Inputs and enabling the device (refer to Chip Enable section). Both the Address Inputs and Data Input/Outputs are latched by the Command Interface on the rising edge of Write Enable or Chip Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole Bus Write operation. See Figures 13, and 14, Write AC Waveforms, and Tables 18 and 19, Write and Chip Enable Controlled Write AC Characteristics, for details of the timing requirements. Output Disable. The Data Inputs/Outputs are in the high impedance state when the Output Enable is High. Standby. When Chip Enable is High, VIH, the device enters Standby mode and the Data Inputs/ Outputs pins are placed in the high impedance state regardless of Output Enable or Write Enable. The Supply Current is reduced to the Standby Supply Current, IDD1. During Program or Erase operations the device will continue to use the Program/Erase Supply Current, IDD3, for Program or Erase operations until the operation completes. Automatic Low Power. If there is no change in the state of the bus for a short period of time during Asynchronous Bus Read operations the device enters Auto Low Power mode where the internal Supply Current is reduced to the Auto-Standby Supply Current, IDD5. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress. Automatic Low Power is only available in Asynchronous Read modes. Power-Down. The device is in Power-Down mode when Reset/Power-Down, RP, is Low. The power consumption is reduced to the Power-Down level, IDD2, and the outputs are high impedance, independent of Chip Enable, Output Enable or Write Enable.
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M30LW128D
Table 4. Bus Operations
Bus Operation Memory Enabled Upper Bus Read Lower Upper Page Read Lower Upper Bus Write Lower Output Disable Standby Power-Down Output disabled Device disabled Device disabled VIL X X X VIL VIH VIL VIH A23 VIH E G W RP A1-A22 (x16) A0-A22 (x8) Address DQ0-DQ15 (x16) DQ0-DQ7 (x8)(1) Data Output
VIL
VIL
VIH
High
VIL
VIL
VIH
High
Address
Data Output
VIL VIL VIH X
VIH VIH X X
VIL VIH X X
High High High VIL
Address X X X
Data Input High Z High Z High Z
Note: 1. DQ8-DQ15 are High Z in x8 mode. 2. X = Don't Care VIL or VIH . High = VIH or VHH.
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M30LW128D
COMMAND INTERFACE All Bus Write operations to the device are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. As the device contains two internal memories care must be taken to issue the commands to the correct address. Commands issued with A23 High will be addressed to the Upper Memory, commands issued with A23 Low will be addressed to the Lower Memory. The Commands are summarized in Table 5, Commands. Refer to Table 5 in conjunction with the text descriptions below. After power-up or a Reset operation the device enters Read mode. Read Memory Array Command. The Read Memory Array command is used to return the device to Read mode. One Bus Write cycle is required to issue the Read Memory Array command and return the device to Read mode. Once the command is issued the device remains in Read mode until another command is issued. From Read mode Bus Read operations will access the memory arrays. After power-up or a reset the device defaults to Read Array mode (Page Read). While the Program/Erase Controller is executing a Program, Erase, Block Protect, Blocks Unprotect or Protection Register Program operation the device will not accept the Read Memory Array command until the operation completes. Read Electronic Signature Command. The Read Electronic Signature command is used to read the Manufacturer Code, the Device Code, the Block Protection Status and the Protection Register. One Bus Write cycle is required to issue the Read Electronic Signature command. Once the command is issued subsequent Bus Read operations read the Manufacturer Code, the Device Code, the Block Protection Status or the Protection Register until another command is issued. Refer to Table 7, Read Electronic Signature, Tables 8 and 9, Word and Byte-wide Read Protection Register and Figure 8, Protection Register Memory Map for information on the addresses. Read Query Command. The Read Query Command is used to read data from the Common Flash Interface (CFI) Memory Area. One Bus Write cycle is required to issue the Read Query Command. Once the command is issued subsequent Bus Read operations read from the Common Flash Interface Memory Area. See Appendix B, Tables 26, 27, 28, 29, 30 and 31 for details on the information contained in the Common Flash Interface (CFI) memory area. Read Status Register Command. The Read Status Register command is used to read the Status Register. One Bus Write cycle is required to issue
the Read Status Register command. As the device contains two Status Registers (one for each internal memory) the command must be issued to the same address as the previous operation (Block Erase, Write to Buffer, Word Program etc.). Once the command is issued subsequent Bus Read operations to the same internal memory (A23 Low or A23 High depending on where the command was issued to) read the Status Register until another command is issued. If the Bus Read operation is issued to the other internal memory, then the other Status Register will be read, giving the status of the last command issued in the other internal memory. The Status Register information is present on the output data bus (DQ1-DQ7) when the device is enabled and Output Enable is Low, V IL. See the section on the Status Register and Table 11 for details on the definitions of the Status Register bits Clear Status Register Command. The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status Register to `0'. One Bus Write is required to issue the Clear Status Register command. The command must be issued to the same address as the previous operation (Block Erase, Write to Buffer, Word Program etc.). The bits in the Status Register are sticky and do not automatically return to `0' when a new Write to Buffer and Program, Erase, Block Protect, Block Unprotect or Protection Register Program command is issued. If any error occurs then it is essential to clear any error bits in the Status Register by issuing the Clear Status Register command before attempting a new Program, Erase or Resume command. Block Erase Command. The Block Erase command can be used to erase a block. It sets all of the bits in the block to `1'. All previous data in the block is lost. If the block is protected then the Erase operation will abort, the data in the block will not be changed and the Status Register will output the error. Two Bus Write operations are required to issue the command; the second Bus Write cycle latches the block address in the internal state machine and starts the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During Erase, the device being erased will only accept the Read Status Register and Program/Erase Suspend commands, ignoring all other commands. The device not being erased will accept
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M30LW128D
any command. Typical Erase times are given in Table 10. See Appendix C, Figure 21, Block Erase Flowchart and Pseudo Code, for a suggested flowchart on using the Block Erase command. Word/Byte Program Command. The Word/ Byte Program command is used to program a single Word or Byte in the memory array. Two Bus Write operations are required to issue the command; the first write cycle sets up the Word Program command, the second write cycle latches the address and data to be programmed in the internal state machine and starts the Program/Erase Controller. If the block being programmed is protected an error will be set in the Status Register and the operation will abort without affecting the data in the memory array. The block must be unprotected using the Blocks Unprotect command. Write to Buffer and Program Command. The Write to Buffer and Program command is used to program the memory array. If the command is issued with A23 High the Upper Memory will be programmed, if the command is issued with A23 Low the Lower Memory will be programmed. Up to 16 Words/32 Bytes can be loaded into the Write Buffer and programmed into the memory array. Each Write Buffer has the same A5-A22 addresses. In Byte-wide mode only A0-A4 may change, in Word-wide mode only A1-A4 may change. Four successive steps are required to issue the command. 1. One Bus Write operation is required to set up the Write to Buffer and Program Command. Issue the set up command with the selected memory Block Address where the program operation should occur (any address in the block where the values will be programmed can be used). Any Bus Read operations will start to output the Status Register after the 1st cycle. 2. Use one Bus Write operation to write the same block address along with the value N on the Data Inputs/Output, where N+1 is the number of Words/Bytes to be programmed. 3. Use N+1 Bus Write operations to load the address and data for each Word into the Write Buffer. The addresses must have the same A5A22. 4. Finally, use one Bus Write operation to issue the final cycle to confirm the command and start the Program operation. Invalid address combinations or failing to follow the correct sequence of Bus Write cycles will set an error in the Status Register and abort the operation without affecting the data in the memory array. The Status Register should be cleared before re-issuing the command. If the block being programmed is protected an error will be set in the Status Register and the operation will abort without affecting the data in the memory array. The block must be unprotected using the Blocks Unprotect command. See Appendix C, Figure 19, Write to Buffer and Program Flowchart and Pseudo Code, for a suggested flowchart on using the Write to Buffer and Program command. Program/Erase Suspend Command. The Program/Erase Suspend command is used to pause a Write to Buffer and Program or Erase operation. The command will only be accepted during a Program or an Erase operation. It can be issued at any time during an Erase operation but will only be accepted during a Write to Buffer and Program command if the Program/Erase Controller is running. One Bus Write cycle is required to issue the Program/Erase Suspend command and pause the Program/Erase Controller. The command must be issued to the same address as the current Program or Erase operation. Once the command is issued it is necessary to poll the Program/Erase Controller Status bit (bit 7) to find out when the Program/Erase Controller has paused; no other commands will be accepted until the Program/ Erase Controller has paused. After the Program/ Erase Controller has paused, the device will continue to output the Status Register until another command is issued. During the polling period between issuing the Program/Erase Suspend command and the Program/ Erase Controller pausing, it is possible for the operation to complete. Once the Program/Erase Controller Status bit (bit 7) indicates that the Program/Erase Controller is no longer active, the Program Suspend Status bit (bit 2) or the Erase Suspend Status bit (bit 6) can be used to determine if the operation has completed or is suspended. For timing on the delay between issuing the Program/Erase Suspend command and the Program/Erase Controller pausing see Table 10. During Program/Erase Suspend the Read Memory Array, Read Status Register, Read Electronic Signature, Read Query and Program/Erase Resume commands will be accepted by the Command Interface. Additionally, if the suspended operation was Erase then the Word Program, Write to Buffer and Program, and Program Suspend commands will also be accepted. When one of the devices is being Program or Erase Suspended, any command issued to the other internal Flash memory will be accepted. When a program operation is completed inside a
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M30LW128D
Block Erase Suspend the Read Memory Array command must be issued to reset the device in Read mode, then the Erase Resume command can be issued to complete the whole sequence. Only the blocks not being erased may be read or programmed correctly. See Appendix C, Figure 20, Program Suspend & Resume Flowchart and Pseudo Code, and Figure 22, Erase Suspend & Resume Flowchart and Pseudo Code, for suggested flowcharts on using the Program/Erase Suspend command. Program/Erase Resume Command. The Program/Erase Resume command can be used to restart the Program/Erase Controller after a Program/Erase Suspend operation has paused it. One Bus Write cycle is required to issue the Program/Erase Resume command. The command must be issued to the same address as the Program/Erase Suspend command. Once the command is issued subsequent Bus Read operations read the Status Register. Block Protect Command. The Block Protect command is used to protect a block and prevent Program or Erase operations from changing the data in it. Two Bus Write cycles are required to issue the Block Protect command; the second Bus Write cycle latches the block address in the internal state machine and starts the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Block Protect operation the device will only accept the Read Status Register command. All other commands will be ignored. Typical Block Protection times are given in Table 10. The Block Protection bits are non-volatile, once set they remain set through reset and powerdown/power-up. They are cleared by a Blocks Unprotect command. See Appendix C, Figure 23, Block Protect Flowchart and Pseudo Code, for a suggested flowchart on using the Block Protect command. Blocks Unprotect Command. The Blocks Unprotect command is used to unprotect all of the blocks. To unprotect all of the blocks in both of the internal memories the command must be issued to both memories, that is first with A23 Low and then with A23 High. Four Bus Write cycles are required to issue the Blocks Unprotect command; the first two are written with A23 Low, the second two are written with A23 High. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Blocks Unprotect operation the device will only accept the Read Status Register command. All other commands will be ignored. Typical Block Protection times are given in Table 10. See Appendix C, Figure 24, Blocks Unprotect Flowchart and Pseudo Code, for a suggested flowchart on using the Blocks Unprotect command. Protection Register Program Command. The Protection Register Program command is used to Program the 64 bit user segment of the Protection Register. Only the lower address Protection Register is available to the customer (A23 Low), the other Protection Register is reserved. Two write cycles are required to issue the Protection Register Program command. s The first bus cycle sets up the Protection Register Program command. s The second latches the Address and the Data to be written to the Protection Register and starts the Program/Erase Controller. Read operations output the Status Register content after the programming has started. The user-programmable segment can be locked by programming bit 1 of the Protection Register Lock location to `0' (see Table 8 and x for Wordwide and Byte-wide protection addressing). Bit 0 of the Protection Register Lock location locks the factory programmed segment and is programmed to `0' in the factory. The locking of the Protection Register is not reversible, once the lock bits are programmed no further changes can be made to the values stored in the Protection Register, see Figure 8, Protection Register Memory Map. Attempting to program a previously protected Protection Register will result in a Status Register error. The Protection Register Program cannot be suspended. See Appendix C, Figure 25, Protection Register Program Flowchart and Pseudo Code, for the flowchart for using the Protection Register Program command. Configure STS Command. The Configure STS command is used to configure the Status/(Ready/Busy) pin. It has to be configured for both internal memories, that is the command has to be issued first with A23 Low and then with A23 High. After power-up or reset the STS pin is configured in Ready/Busy mode. The pin can be configured in Status mode using the Configure STS command (refer to Status/(Ready/Busy) section for more details. Four Bus Write cycles are required to issue the Configure STS command. The first two cycles
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M30LW128D
must be written with A23 Low and the second two with A23 High. s The first bus cycle sets up the Configure STS command. A23 must be Low. s The second Bus Write cycle specifies one of the four possible configurations, A23 must be Low, (refer to Table 6, Configuration Codes): - Ready/Busy mode - Pulse on Erase complete mode - Pulse on Program complete mode - Pulse on Erase or Program complete mode The third Bus Write cycle re-sets up the Configure STS command. This time A23 must be High. s The fourth re-specifies the configuration code given in the second Bus Write cycle. A23 must be High. The device will not accept the Configure STS command while the Program/Erase controller is busy or during Program/Erase Suspend. When STS pin is pulsing it remains Low for a typical time of 250ns. Any invalid Configuration Code will set an error in the Status Register. The Configure STS command is not available with the LFBGA88 package.
s
Table 5. Commands
Command Cycles Bus Operations 1st Cycle Op. Write Addr. RA X PA/BA X PA/BA BA PA BA PA/BA PA/BA BA Data Op. FFh Read 90h Read 70h Read 98h Read 50h 20h Write 40h Write 10h E8h Write B0h D0h 60h Write BA 01h D0h PRD CC Write 400000h B8h Write 400000h CC Write 400000h 60h Write 400000h D0h BA PA BA D0 PD N Write PA PD Write BA D0h 2nd Cycle Addr. RA IDA(2) PA/BA QA(3) Data RD IDD(2) SRD QD(3) Subsequent Op. Addr. Data Op. Final Addr. Data
Read Memory Array Read Electronic Signature Read Status Register Read Query Clear Status Register Block Erase Word/Byte Program
2
2 Write 2 Write
2 Write 1 2 2 Write Write Write
Write to Buffer and 4+N Write Program Program/Erase Suspend Program/Erase Resume Block Protect Blocks Unprotect Protection Register Program Configure STS command(4) 1 1 2 4 2 4 Write Write Write
Write 000000h 60h Write 000000h Write PRA C0h Write PRA
Write 000000h B8h Write 000000h
Note: 1. X Don't Care; RA Read Address, RD Read Data, IDA Identifier Address, IDD Identifier Data, SRD Status Register Data, PA Program Address, PD Program Data, QA Query Address, QD Query Data, BA Any address in Block, PRA Protection register address, PRD Protection Register Data, CC Configuration Code. The shaded areas highlight the differences with a single M58LW064D memory. 2. For Identifier addresses and data refer to Table 7, Read Electronic Signature. 3. For Query Address and Data refer to Appendix B, CFI. 4. Not available with LFBGA88 package.
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Table 6. Configuration Codes
Configuration Code DQ1 DQ2 Mode STS Pin VOL during P/E operations Hi-Z when the memory is ready Description The STS pin is Low during Program and Erase operations and high impedance when the memory is ready for any Read, Program or Erase operation. Supplies a system interrupt pulse at the end of a Block Erase operation. Pulse Low then High when operation completed(2) Supplies a system interrupt pulse at the end of a Program operation. Supplies a system interrupt pulse at the end of a Block Erase or Program operation.
00h
0
0
Ready/Busy
01h
0
1
Pulse on Erase complete Pulse on Program complete Pulse on Erase or Program complete
02h
1
0
03h
1
1
Note: 1. DQ2-DQ7 are reserved 2. When STS pin is pulsing it remains Low for a typical time of 250ns.
Table 7. Read Electronic Signature
Code Manufacturer Code x16 x8 Device Code x16 x8 Block Protection Status x16 Protection Register x8, x16 000080h(2) SBA(1)+02h 000001h 8817h 00h (Block Unprotected) 01h (Block Protected) 0000h (Block Unprotected) 0001h (Block Protected) PRD(1) Bus Width x8 000000h 0020h 17h Address (A23-A1)(3) Data (DQ15-DQ0) 20h
Note: 1. SBA is the Start Base Address of each block, PRD is Protection Register Data. 2. Base Address, refer to Figure 8 and Tables 8 and 9 for more information. A23 must be Low to address the customer's Protection Register. The other Protection Register is reserved. 3. A0 is not used in Read Electronic Signature in either x8 or x16 mode. The data is always presented on the lower byte in x16 m ode.
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Figure 8. Protection Register Memory Map
WORD ADDRESS 88h User Programmable 85h 84h Unique device number 81h 80h Protection Register Lock 1 0
AI05501
Table 8. Word-Wide Read Protection Register
Word Lock 0 1 2 3 4 5 6 7 Use Factory, User Factory (Unique ID) Factory (Unique ID) Factory (Unique ID) Factory (Unique ID) User User User User A8 1 1 1 1 1 1 1 1 1 A7 0 0 0 0 0 0 0 0 0 A6 0 0 0 0 0 0 0 0 0 A5 0 0 0 0 0 0 0 0 0 A4 0 0 0 0 0 0 0 0 1 A3 0 0 0 0 1 1 1 1 0 A2 0 0 1 1 0 0 1 1 0 A1 0 1 0 1 0 1 0 1 0
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Table 9. Byte-Wide Read Protection Register
Word Lock Lock 0 1 2 3 4 5 6 7 8 9 A B C D E F Use Factory, User Factory, User Factory (Unique ID) Factory (Unique ID) Factory (Unique ID) Factory (Unique ID) Factory (Unique ID) Factory (Unique ID) Factory (Unique ID) Factory (Unique ID) User User User User User User User User A8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
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Table 10. Program/Erase Times and Program/Erase Endurance Cycles
M30LW128D Parameters Min Block (1Mb) Erase Chip Program (Write to Buffer) Chip Erase Time Program Write Buffer Word/Byte Program Time (Word/Byte Program command) Program Suspend Latency Time Erase Suspend Latency Time Block Protect Time Blocks Unprotect Time Program/Erase Cycles (per block) Data Retention
Note: 1. 2. 3. 4. 5.
Typ(1,2) 1.2 98 148 192 (3) 16 1 1 18 0.75
Max(2) 4.8(4) 290(4) 440 (4) 576 (4) 48 (4) 20 (5) 25 (5) 30 (5) 1.2 (5)
Unit s s s s s s s s s cycles years
100,000 20
Typical values measured at room temperature and nominal voltages. Sampled, but not 100% tested. Effective byte programming time 6s, effective word programming time 12s. Maximum value measured at worst case conditions for both temperature and VDD after 100,000 program/erase cycles. Maximum value measured at worst case conditions for both temperature and VDD.
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STATUS REGISTER The Status Register provides information on the current or previous Program, Erase, Block Protect or Blocks Unprotect operation. The various bits in the Status Register convey information and errors on the operation. They are output on DQ7-DQ0. To read the Status Register the Read Status Register command can be issued. The Status Register is automatically read after Program, Erase, Block Protect, Blocks Unprotect and Program/Erase Resume commands. As the device contains two Status Registers (one for each internal memory) the Status Register must be read at the same address as the previous operation. The contents of the Status Register can be updated during an Erase or Program operation by toggling the Output Enable pin or by dis-activating and then reactivating the device (refer to Table 3). Status Register bits 5, 4, 3 and 1 are associated with various error conditions and can only be reset with the Clear Status Register command. The Status Register bits are summarized in Table 11, Status Register Bits. Refer to Table 11 in conjunction with the following text descriptions. Program/Erase Controller Status (Bit 7). The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive. When the Program/Erase Controller Status bit is Low, VOL, the Program/Erase Controller is active and all other Status Register bits are High Impedance; when the bit is High, VOH, the Program/ Erase Controller is inactive. The Program/Erase Controller Status is Low immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the bit is High. During Program, Erase, Block Protect and Blocks Unprotect operations the Program/Erase Controller Status bit can be polled to find the end of the operation. The other bits in the Status Register should not be tested until the Program/Erase Controller completes the operation and the bit is High. After the Program/Erase Controller completes its operation the Erase Status, Program Status and Block Protection Status bits should be tested for errors. Erase Suspend Status (Bit 6). The Erase Suspend Status bit indicates that an Erase operation has been suspended and is waiting to be resumed. The Erase Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive); after a Program/Erase Suspend command is issued the memory may still complete the operation rather than entering the Suspend mode.
When the Erase Suspend Status bit is Low, V OL, the Program/Erase Controller is active or has completed its operation; when the bit is High, VOH, a Program/Erase Suspend command has been issued and the memory is waiting for a Program/ Erase Resume command. When a Program/Erase Resume command is issued the Erase Suspend Status bit returns Low. Erase Status (Bit 5). The Erase Status bit can be used to identify if the device has failed to verify that the block has erased correctly or that all blocks have been unprotected successfully. The Erase Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). When the Erase Status bit is Low, V OL, the device has successfully verified that the block has erased correctly or all blocks have been unprotected successfully. When the Erase Status bit is High, VOH, the erase operation has failed. Depending on the cause of the failure other Status Register bits may also be set to High, VOH. s If only the Erase Status bit (bit 5) is set High, VOH, then the Program/Erase Controller has applied the maximum number of pulses to the block and still failed to verify that the block has erased correctly or that all the blocks have been unprotected successfully. s If the failure is due to an erase or blocks unprotect with VPEN low, VOL, then VPEN Status bit (bit 3) is also set High, VOH. s If the failure is due to an erase on a protected block then Block Protection Status bit (bit 1) is also set High, VOH. s If the failure is due to a program or erase incorrect command sequence then Program Status bit (bit 4) is also set High, VOH. Once set High, the Erase Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Program Status (Bit 4). The Program Status bit is used to identify a Program or Block Protect failure. The Program Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). When the Program Status bit is Low, V OL, the device has successfully verified that the Write Buffer has programmed correctly or the block is protected. When the Program Status bit is High, V OH, the program or block protect operation has failed. Depending on the cause of the failure other Status Register bits may also be set to High, VOH.
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If only the Program Status bit (bit 4) is set High, VOH, then the Program/Erase Controller has applied the maximum number of pulses to the byte and still failed to verify that the Write Buffer has programmed correctly or that the Block is protected. s If the failure is due to a program or block protect with VPEN low, VOL, then VPEN Status bit (bit 3) is also set High, VOH. s If the failure is due to a program on a protected block then Block Protection Status bit (bit 1) is also set High, VOH. s If the failure is due to a program or erase incorrect command sequence then Erase Status bit (bit 5) is also set High, VOH. Once set High, the Program Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. VPEN Status (Bit 3). The VPEN Status bit can be used to identify if a Program, Erase, Block Protection or Block Unprotection operation has been attempted when VPEN is Low, VIL. When the VPEN Status bit is Low, VOL, no Program, Erase, Block Protection or Block Unprotection operations have been attempted with VPEN Low, VIL, since the last Clear Status Register command, or hardware reset. When the VPEN Status bit is High, VOH, a Program, Erase, Block Protection or Block Unprotection operation has been attempted with VPEN Low, VIL. Once set High, the VPEN Status bit can only be reset by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program, Erase, Block Protection or Block Unprotection command is issued, otherwise the new command will appear to fail.
s
Program Suspend Status (Bit 2). The Program Suspend Status bit indicates that a Program operation has been suspended and is waiting to be resumed. The Program Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive); after a Program/Erase Suspend command is issued the device may still complete the operation rather than entering the Suspend mode. When the Program Suspend Status bit is Low, VOL, the Program/Erase Controller is active or has completed its operation; when the bit is High, VOH, a Program/Erase Suspend command has been issued and the device is waiting for a Program/ Erase Resume command. When a Program/Erase Resume command is issued the Program Suspend Status bit returns Low. Block Protection Status (Bit 1). The Block Protection Status bit can be used to identify if a Program or Erase operation has tried to modify the contents of a protected block. When the Block Protection Status bit is Low, V OL, no Program or Erase operations have been attempted to protected blocks since the last Clear Status Register command or hardware reset; when the Block Protection Status bit is High, VOH, a Program (Program Status bit 4 set High) or Erase (Erase Status bit 5 set High) operation has been attempted on a protected block. Once set High, the Block Protection Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Reserved (Bit 0). Bit 0 of the Status Register is reserved. Its value should be masked.
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Table 11. Status Register Bits
OPERATION Program/Erase Controller active Write Buffer not ready Write Buffer ready Write Buffer ready in Erase Suspend Program suspended Program suspended in Erase Suspend Program/Block Protect completed successfully Program completed successfully in Erase Suspend Program/Block protect failure due to incorrect command sequence Program failure due to incorrect command sequence in Erase Suspend Program/Block Protect failure due to VPEN error Program failure due to VPEN error in Erase Suspend Program failure due to Block Protection Program failure due to Block Protection in Erase Suspend Program/Block Protect failure due to cell failure Program failure due to cell failure in Erase Suspend Erase Suspended Erase/Blocks Unprotect completed successfully Erase/Blocks Unprotect failure due to incorrect command sequence Erase/Blocks Unprotect failure due to VPEN error Erase failure due to Block Protection Erase/Blocks Unprotect failure due to failed cells in Block Configure STS error due to invalid configuration code Bit 7 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 0 0 0 1 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Result (Hex) N/A N/A 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 80h C0h 84h C4h 80h C0h B0h F0h 98h D8h 92h D2h 90h D0h C0h 80h B0h A8h A2h A0h B0h
Hi-Z Hi-Z
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MAXIMUM RATING Stressing the device above the ratings listed in Table 12, Absolute Maximum Ratings, may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is Table 12. Absolute Maximum Ratings
Value Symbol TBIAS TSTG VIO VDD, VDDQ IOSC Parameter Min Temperature Under Bias Storage Temperature Input or Output Voltage Supply Voltage Output Short-circuit Current -40 -55 -0.6 -0.6 Max 125 150 VDDQ +0.6 5.0 100(1) C C V V mA Unit
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Note: 1. Maximum one output short-circuited at a time and for no longer than 1 second.
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DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measure-
ment Conditions summarized in Table 13, Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters.
Table 13. Operating and AC Measurement Conditions
M30LW128D Parameter Min Supply Voltage (VDD) Input/Output Supply Voltage (VDDQ) Grade 1 Ambient Temperature (TA) Grade 6 Load Capacitance (CL) Input Pulses Voltages Input and Output Timing Ref. Voltages -40 30 0 to VDDQ 0.5 VDDQ 85 C pF V V 2.7 2.7 0 Max 3.6 3.6 70 V V C Units
Figure 9. AC Measurement Input Output Waveform
Figure 10. AC Measurement Load Circuit
1.3V
1N914 VDDQ VDD VDDQ 0.5 VDDQ 0V
AI00610
3.3k DEVICE UNDER TEST CL 0.1F 0.1F CL includes JIG capacitance
AI03459
DQS
Table 14. Capacitance
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Typ 6 8 Max 8 12 Unit pF pF
Note: 1. TA = 25C, f = 1 MHz 2. Sampled only, not 100% tested.
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Table 15. DC Characteristics
Symbol ILI ILO IDD IDDO IDD1 IDD5 IDD2 IDD3 IDD4 VIL VIH VOL VOH VLKO VPENH Parameter Input Leakage Current Output Leakage Current Supply Current (Random Read) Supply Current (Page Read) Supply Current (Standby) Supply Current (Auto Low-Power) Supply Current (Reset/Power-Down) Supply Current (Program or Erase, Block Protect, Block Unprotect) Supply Current (Erase/Program Suspend) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VDD Supply Voltage (Erase and Program lockout) VPEN Supply Voltage (block erase, program and block protect) 2.7 IOL = 100A IOH = -100A VDDQ -0.2 2 3.6 Test Condition 0V VIN VDDQ 0V VOUT VDDQ E = VIL, f=5MHz E = VIL, f=33MHz E = VIH, RP = VIH E = VIL, RP = VIH RP = VIL Program or Erase operation in progress E = VIH -0.5 0.7VDDQ Min Max 1 5 20 29 80 80 80 30 80 0.3VDDQ VDDQ + 0.5 0.2 Unit A A mA mA A A A mA A V V V V V V
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Figure 11. Bus Read AC Waveforms
tAVAV A0-A23 tELQV tELQX E
(1)
VALID
tAXQX
tGLQV tGLQX G tELBL BYTE (2) tBLQV tBLQZ tAVQV DQ0-DQ15 OUTPUT
tEHQZ tEHQX
tGHQX
tGHQZ
AI07509
Note: 1. Refer to Table 3 for details of how the device is enabled. 2. BYTE can be Low or High. The BYTE signal is not available with the LFBGA88 package.
Table 16. Bus Read AC Characteristics
M30LW128D Symbol tAVAV tAVQV tAXQX tBLQV tBLQZ tEHQX tEHQZ tELBL tELQX tELQV tGHQX tGHQZ tGLQX tGLQV Parameter Address Valid to Address Valid Address Valid to Output Valid Address Transition to Output Transition Byte Low (or High) to Output Valid Byte Low (or High) to Output Hi-Z Chip Enable High to Output Transition Chip Enable High to Output Hi-Z Chip Enable Low to Byte Low (or High) Chip Enable Low to Output Transition Chip Enable Low to Output Valid Output Enable High to Output Transition Output Enable High to Output Hi-Z Output Enable Low to Output Transition Output Enable Low to Output Valid Test Condition 110 E = VIL, G = VIL E = VIL, G = VIL E = VIL, G = VIL E = VIL, G = VIL E = VIL, G = VIL G = VIL G = VIL G = VIL G = VIL G = VIL E = VIL E = VIL E = VIL E = VIL Min Max Min Max Max Min Max Max Min Max Min Max Min Max 110 110 0 1 1 0 25 10 0 110 0 15 0 25 ns ns ns s s ns ns ns ns ns ns ns ns ns Unit
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Figure 12. Page Read AC Waveforms
A1-A2 A3-A23 tAVQV tELQV E (1) tGLQV tGLQX G tGHQZ tELQX DQ0-DQ15 OUTPUT tGHQX OUTPUT tAVQV1 tAXQX1 tEHQZ tEHQX tAXQX VALID VALID VALID
AI07510
Note: 1. Refer to Table 3 for details of how the device is enabled.
Table 17. Page Read AC Characteristics
M30LW128D Symbol tAXQX1 tAVQV1 Parameter Address Transition to Output Transition Address Valid to Output Valid Test Condition 110 E = VIL, G = VIL E = VIL, G = VIL Min Max 6 25 ns ns Unit
Note: For other timings see Table 16, Bus Read AC Characteristics.
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Figure 13. Write AC Waveform, Write Enable Controlled
A0-A23 tAVWH E (1) tELWL G tGHWL W
VALID tWHAX
tWHEH
tWLWH
tWHWL
tWHGL
tDVWH DQ0-DQ15 STS(2) (Ready/Busy mode) tVPHWH VPEN
AI07511
INPUT tWHDX
tWHBL
Note: 1. Refer to Table 3 for details of how the device is enabled. 2. Not available with the LFBGA88 package.
Table 18. Write AC Characteristics, Write Enable Controlled
M30LW128D Symbol tAVWH tDVWH tELWL tVPHWH tWHAX tWHBL tWHDX tWHEH tGHWL tWHGL tWHWL tWLWH Parameter Address Valid to Write Enable High Data Input Valid to Write Enable High Chip Enable Low to Write Enable Low Program/Erase Enable High to Write Enable High Write Enable High to Address Transition Write Enable High to Status/(Ready/Busy) low Write Enable High to Input Transition Write Enable High to Chip Enable High Output Enable High to Write Enable Low Write Enable High to Output Enable Low Write Enable High to Write Enable Low Write Enable Low to Write Enable High E = VIL E = VIL E = VIL Test Condition 110 E = VIL E = VIL Min Min Min Min Min Max Min Min Min Min Min Min 50 50 0 0 0 500 0 0 20 35 30 70 ns ns ns ns ns ns ns ns ns ns ns ns Unit
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Figure 14. Write AC Waveforms, Chip Enable Controlled
A0-A23 tAVEH W tWLEL G tGHEL E (1)
VALID tEHAX
tEHWH
tELEH
tEHEL
tEHGL
tDVEH DQ0-DQ15 INPUT tEHDX STS(2) (Ready/Busy mode) tVPHEH VPEN
AI07512
tEHBL
Note: 1. Refer to Table 3 for details of how the device is enabled. 2. Not available with the LFBGA88 package.
Table 19. Write AC Characteristics, Chip Enable Controlled.
M30LW128D Symbol tAVEH tDVEH tWLEL tVPHEH tEHAX tEHBL tEHDX tEHWH tGHEL tEHGL tEHEL tELEH Parameter Address Valid to Chip Enable High Data Input Valid to Chip Enable High Write Enable Low to Chip Enable Low Program/Erase Enable High to Chip Enable High Chip Enable High to Address Transition Chip Enable High to Status/(Ready/Busy) low Chip Enable High to Input Transition Chip Enable High to Write Enable High Output Enable High to Chip Enable Low Chip Enable High to Output Enable Low Chip Enable High to Chip Enable Low Chip Enable Low to Chip Enable High W = VIL W = VIL W = VIL Test Condition 110 W = VIL W = VIL Min Min Min Min Min Max Min Min Min Min Min Min 50 50 0 0 5 500 5 0 20 35 30 70 ns ns ns ns ns ns ns ns ns ns ns ns Unit
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Figure 15. Reset, Power-Down and Power-Up AC Waveform
W tPHWL E (1), G
DQ0-DQ15 tPHQV STS(2) (Ready/Busy mode) tPLBH RP tVDHPH VDD, VDDQ Power-Up and Reset Reset during Program or Erase
AI07513b
tPLPH
Note: 1. Refer to Table 3 for details of how the device is enabled. 2. Not available with the LFBGA88 package.
Table 20. Reset, Power-Down and Power-Up AC Characteristics
M30LW128D Symbol tPHQV tPHWL tPLPH tPLBH tVDHPH Parameter 110 Reset/Power-Down High to Data Valid Reset/Power-Down High to Write Enable Low Reset/Power-Down Low to Reset/Power-Down High Reset/Power-Down Low to Status/(Ready/Busy) High Supply Voltages High to Reset/Power-Down High Max Max Min Max Min 150 1 100 30 0 ns s ns s s Unit
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PACKAGE MECHANICAL Figure 16. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Outline
A2
1 N
e E B
N/2
D1 D
A CP
DIE
C
TSOP-a
A1
L
Note: Drawing is not to scale.
Table 21. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Mechanical Data
mm Symbol Typ A A1 A2 B C D D1 E e L N CP 0.50 0.05 0.95 0.17 0.10 19.80 18.30 13.90 - 0.50 0 56 0.10 Min Max 1.20 0.15 1.05 0.27 0.21 20.20 18.50 14.10 - 0.70 5 0.0197 0.0020 0.0374 0.0067 0.0039 0.7795 0.7205 0.5472 - 0.0197 0 56 0.0039 Typ Min Max 0.0472 0.0059 0.0413 0.0106 0.0083 0.7953 0.7283 0.5551 - 0.0276 5 inches
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Figure 17. TBGA64 - 10x13mm, 8 x 8 ball array 1mm pitch, Package Outline
D FD FE D1 SD
E
E1
SE
ddd BALL "A1"
A
e
b A1
A2
BGA-Z23
Note: Drawing is not to scale.
Table 22. TBGA64 - 10x13mm, 8 x 8 ball array, 1 mm pitch, Package Mechanical Data
millimeters Symbol Typ A A1 A2 b D D1 ddd e E E1 FD FE SD SE 1.000 13.000 7.000 1.500 3.000 0.500 0.500 - 12.900 - - - - - 10.000 7.000 0.400 9.900 - 0.300 0.200 Min Max 1.200 0.350 0.850 0.500 10.100 - 0.100 - 13.100 - - - - - 0.0394 0.5118 0.2756 0.0591 0.1181 0.0197 0.0197 - 0.5079 - - - - - 0.3937 0.2756 0.0157 0.3898 - 0.0118 0.0079 Typ Min Max 0.0472 0.0138 0.0335 0.0197 0.3976 - 0.0039 - 0.5157 - - - - - inches
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Figure 18. LFBGA88 8x10 mm - 8x10 ball array, 0.8mm pitch, Bottom View Package Outline
D D1
e SE E E2 E1 b BALL "A1"
ddd FE1 FE FD A A1 SD A2
BGA-Z42
Note: Drawing is not to scale.
Table 23. LFBGA88 8x10mm - 8x10 ball array, 0.8mm pitch, Package Mechanical Data
millimeters Symbol Typ A A1 A2 b D D1 ddd E E1 E2 e FD FE FE1 SD SE 10.000 7.200 8.800 0.800 1.200 1.400 0.600 0.400 0.400 9.900 - - - - - - - - 0.960 0.400 8.000 5.600 0.350 7.900 - 0.450 8.100 - 0.100 10.100 - - - - - - - - 0.3937 0.2835 0.3465 0.0315 0.0472 0.0551 0.0236 0.0157 0.0157 0.3898 - - - - - - - - 0.300 0.0378 0.0157 0.3150 0.2205 0.0138 0.3110 - 0.0177 0.3189 - 0.0039 0.3976 - - - - - - - - Min Max 1.400 0.0118 Typ Min Max 0.0551 inches
Note: All of the values in the table are preliminary and are subject to change.
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PART NUMBERING Table 24. Ordering Information Scheme
Example: Device Type M30 = Multiple Memory Product, Multiple Flash Architecture L = Page Mode Operating Voltage W = VDD = 2.7V to 3.6V, VDDQ = 1.8V to VDD Device Function 128D = Two 64 Mbit (x8, x16), Uniform Block Speed 110 = 110 ns Package N = TSOP56: 14 x 20 mm ZA = TBGA64: 10 x 13 mm, 1mm pitch ZE = LFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch Temperature Range 1 = 0 to 70 C 6 = -40 to 85 C Option T = Tape & Reel Packing M30LW128D 110 N 1 T
Note: Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
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M30LW128D
APPENDIX A. BLOCK ADDRESS TABLE Table 25. Block Addresses
Block No. 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 Upper Memory 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 Address Range (x8 Bus Width) FE0000h-FFFFFFh FC0000h-FDFFFFh FA0000h-FBFFFFh F80000h-F9FFFFh F60000h-F7FFFFh F40000h-F5FFFFh F20000h-F3FFFFh F00000h-F1FFFFh EE0000h-EFFFFFh EC0000h-EDFFFFh EA0000h-EBFFFFh E80000h-E9FFFFh E60000h-E7FFFFh E40000h-E5FFFFh E20000h-E3FFFFh E00000h-E1FFFFh DE0000h-DFFFFFh DC0000h-DDFFFFh DA0000h-DBFFFFh D80000h-D9FFFFh D60000h-D7FFFFh D40000h-D5FFFFh D20000h-D3FFFFh D00000h-D1FFFFh CE0000h-CFFFFFh CC0000h-CDFFFFh CA0000h-CBFFFFh C80000h-C9FFFFh C60000h-C7FFFFh C40000h-C5FFFFh C20000h-C3FFFFh C00000h-C1FFFFh BE0000h-BFFFFFh Address Range (x16 Bus Width) 7F0000h-7FFFFFh 7E0000h-7EFFFFh 7D0000h-7DFFFFh 7C0000h-7CFFFFh 7B0000h-7BFFFFh 7A0000h-7AFFFFh 790000h-79FFFFh 780000h-78FFFFh 770000h-77FFFFh 760000h-76FFFFh 750000h-75FFFFh 740000h-74FFFFh 730000h-73FFFFh 720000h-72FFFFh 710000h-71FFFFh 700000h-70FFFFh 6F0000h-6FFFFFh 6E0000h-6EFFFFh 6D0000h-6DFFFFh 6C0000h-6CFFFFh 6B0000h-6BFFFFh 6A0000h-6AFFFFh 690000h-69FFFFh 680000h-68FFFFh 670000h-67FFFFh 660000h-66FFFFh 650000h-65FFFFh 640000h-64FFFFh 630000h-63FFFFh 620000h-62FFFFh 610000h-61FFFFh 600000h-60FFFFh 5F0000h-5FFFFFh Upper Memory Block No. 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 Address Range (x8 Bus Width) BC0000h-BDFFFFh BA0000h-BBFFFFh B80000h-B9FFFFh B60000h-B7FFFFh B40000h-B5FFFFh B20000h-B3FFFFh B00000h-B1FFFFh AE0000h-AFFFFFh AC0000h-ADFFFFh AA0000h-ABFFFFh A80000h-A9FFFFh A60000h-A7FFFFh A40000h-A5FFFFh A20000h-A3FFFFh A00000h-A1FFFFh 9E0000h-9FFFFFh 9C0000h-9DFFFFh 9A0000h-9BFFFFh 980000h-99FFFFh 960000h-97FFFFh 940000h-95FFFFh 920000h-93FFFFh 900000h-91FFFFh 8E0000h-8FFFFFh 8C0000h-8DFFFFh 8A0000h-8BFFFFh 880000h-89FFFFh 860000h-87FFFFh 840000h-85FFFFh 820000h-83FFFFh 800000h-81FFFFh Address Range (x16 Bus Width) 5E0000h-5EFFFFh 5D0000h-5DFFFFh 5C0000h-5CFFFFh 5B0000h-5BFFFFh 5A0000h-5AFFFFh 590000h-59FFFFh 580000h-58FFFFh 570000h-57FFFFh 560000h-56FFFFh 550000h-55FFFFh 540000h-54FFFFh 530000h-53FFFFh 520000h-52FFFFh 510000h-51FFFFh 500000h-50FFFFh 4F0000h-4FFFFFh 4E0000h-4EFFFFh 4D0000h-4DFFFFh 4C0000h-4CFFFFh 4B0000h-4BFFFFh 4A0000h-4AFFFFh 490000h-49FFFFh 480000h-48FFFFh 470000h-47FFFFh 460000h-46FFFFh 450000h-45FFFFh 440000h-44FFFFh 430000h-43FFFFh 420000h-42FFFFh 410000h-41FFFFh 400000h-40FFFFh
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Address Range (x8 Bus Width) 7E0000h-7FFFFFh 7C0000h-7DFFFFh 7A0000h-7BFFFFh 780000h-79FFFFh 760000h-77FFFFh 740000h-75FFFFh 720000h-73FFFFh 700000h-71FFFFh 6E0000h-6FFFFFh 6C0000h-6DFFFFh 6A0000h-6BFFFFh 680000h-69FFFFh 660000h-67FFFFh 640000h-65FFFFh 620000h-63FFFFh 600000h-61FFFFh 5E0000h-5FFFFFh 5C0000h-5DFFFFh 5A0000h-5BFFFFh 580000h-59FFFFh 560000h-57FFFFh 540000h-55FFFFh 520000h-53FFFFh 500000h-51FFFFh 4E0000h-4FFFFFh 4C0000h-4DFFFFh 4A0000h-4BFFFFh 480000h-49FFFFh 460000h-47FFFFh 440000h-45FFFFh 420000h-43FFFFh 400000h-41FFFFh 3E0000h-3FFFFFh 3C0000h-3DFFFFh 3A0000h-3BFFFFh Address Range (x16 Bus Width) 3F0000h-3FFFFFh 3E0000h-3EFFFFh 3D0000h-3DFFFFh 3C0000h-3CFFFFh 3B0000h-3BFFFFh 3A0000h-3AFFFFh 390000h-39FFFFh 380000h-38FFFFh 370000h-37FFFFh 360000h-36FFFFh 350000h-35FFFFh 340000h-34FFFFh 330000h-33FFFFh 320000h-32FFFFh 310000h-31FFFFh 300000h-30FFFFh 2F0000h-2FFFFFh 2E0000h-2EFFFFh 2D0000h-2DFFFFh 2C0000h-2CFFFFh 2B0000h-2BFFFFh 2A0000h-2AFFFFh 290000h-29FFFFh 280000h-28FFFFh 270000h-27FFFFh 260000h-26FFFFh 250000h-25FFFFh 240000h-24FFFFh 230000h-23FFFFh 220000h-22FFFFh 210000h-21FFFFh 200000h-20FFFFh 1F0000h-1FFFFFh 1E0000h-1EFFFFh 1D0000h-1DFFFFh Lower Memory Address Range (x8 Bus Width) 380000h-39FFFFh 360000h-37FFFFh 340000h-35FFFFh 320000h-33FFFFh 300000h-31FFFFh 2E0000h-2FFFFFh 2C0000h-2DFFFFh 2A0000h-2BFFFFh 280000h-29FFFFh 260000h-27FFFFh 240000h-25FFFFh 220000h-23FFFFh 200000h-21FFFFh 1E0000h-1FFFFFh 1C0000h-1DFFFFh 1A0000h-1BFFFFh 180000h-19FFFFh 160000h-17FFFFh 140000h-15FFFFh 120000h-13FFFFh 100000h-11FFFFh 0E0000h-0FFFFFh 0C0000h-0DFFFFh 0A0000h-0BFFFFh 080000h-09FFFFh 060000h-07FFFFh 040000h-05FFFFh 020000h-03FFFFh 000000h-01FFFFh Address Range (x16 Bus Width) 1C0000h-1CFFFFh 1B0000h-1BFFFFh 1A0000h-1AFFFFh 190000h-19FFFFh 180000h-18FFFFh 170000h-17FFFFh 160000h-16FFFFh 150000h-15FFFFh 140000h-14FFFFh 130000h-13FFFFh 120000h-12FFFFh 110000h-11FFFFh 100000h-10FFFFh 0F0000h-0FFFFFh 0E0000h-0EFFFFh 0D0000h-0DFFFFh 0C0000h-0CFFFFh 0B0000h-0BFFFFh 0A0000h-0AFFFFh 090000h-09FFFFh 080000h-08FFFFh 070000h-07FFFFh 060000h-06FFFFh 050000h-05FFFFh 040000h-04FFFFh 030000h-03FFFFh 020000h-02FFFFh 010000h-01FFFFh 000000h-00FFFFh
Block No. 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Lower Memory 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30
Block No. 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
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APPENDIX B. COMMON FLASH INTERFACE - CFI The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the deTable 26. Query Structure Overview
Address x16 0000h 0001h 0010h 001Bh 0027h P(h)(1) A(h)(2) (SBA+02)h
Note: 1. 2. 3. 4.
vice, enabling the software to upgrade itself when necessary. When the CFI Query Command (RCFI) is issued the device enters CFI Query mode and the data structure is read from the memory. Tables 26, 27, 28, 29, 30 and 31 show the addresses used to retrieve the data.
x8(4) 10h 11h 20h 36h 4Eh
Sub-section Name
Description Manufacturer Code Device Code
CFI Query Identification String System Interface Information Device Geometry Definition Primary Algorithm-specific Extended Query Table Alternate Algorithm-specific Extended Query Table Block Status Register
Command set ID and algorithm data offset Device timing and voltage information Flash memory layout Additional information specific to the Primary Algorithm (optional) Additional information specific to the Alternate Algorithm (optional) Block-related Information
Offset 15h defines P which points to the Primary Algorithm Extended Query Address Table. Offset 19h defines A which points to the Alternate Algorithm Extended Query Address Table. SBA is the Start Base Address for each block. In x8 mode A0 must be set to V IL. Otherwise, 00h will be output.
Table 27. CFI - Query Address and Data Output
Address Data x16 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah
(2)
Description "Q" "R" "Y" Query ASCII String
x8(3) 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h 51h 52h 59h 01h 00h 31h Primary algorithm extended Query Address Table: P(h) 00h 00h 00h 00h Alternate Algorithm Extended Query address Table 00h Alternate Vendor: Command Set and Control Interface ID Code 51h; "Q" 52h; "R" 59h; "Y"
Primary Vendor: Command Set and Control Interface ID Code
Note: 1. Query Data are always presented on DQ7-DQ0. DQ15-DQ8 are set to '0'. 2. Offset 19h defines A which points to the Alternate Algorithm Extended Query Address Table. 3. In x8 mode A0 must be set to V IL. Otherwise, 00h will be output.
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Table 28. CFI - Device Voltage and Timing Specification
Address Data x16 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h
Note: 1. 2. 3. 4.
Description VDD Min, 2.7V VDD max, 3.6V VPP min - Not Available VPP max - Not Available 2n s typical time-out for Word, DWord prog - Not Available 2n s, typical time-out for max buffer write 2n ms, typical time-out for Erase Block 2n ms, typical time-out for chip erase - Not Available 2n x typical for Word Dword time-out max - Not Available 2n x typical for buffer write time-out max 2n x typical for individual block erase time-out maximum 2n x typical for chip erase max time-out - Not Available
x8(4) 36h 38h 3Ah 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch 27h (1) 36h (1) 00h (2) 00h (2) 04h 08h 0Ah 00h (3) 04h 04h 04h 00h (3)
Bits are coded in Binary Code Decimal, bit7 to bit4 are scaled in Volts and bit3 to bit0 in mV. Bit7 to bit4 are coded in Hexadecimal and scaled in Volts while bit3 to bit0 are in Binary Code Decimal and scaled in 100mV. Not supported. In x8 mode A0 must be set to V IL. Otherwise, 00h will be output.
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Table 29. Device Geometry Definition
Address Data x16 0027h x8(1) 4Eh 50h 0028h Device Interface N/A(2) 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 52h 54h 56h 58h 5Ah 5Ch 5Eh 60h 01h 00h 05h 00h 01h 7Fh Number (n-1) of Erase Blocks of identical size; n=128 00h 00h 02h Erase Block Region Information x 256 bytes per Erase block (128K bytes) Maximum number of bytes in Write Buffer, 2n Bit7-0 = number of Erase Block Regions in device 18h 02h n where 2n is number of bytes memory Size 02h is the interface for M30LW128D devices delivered in TSOP56 and TBGA64 packages (x8 and x16 modes available) 01h is the interface for M30LW128D devices delivered in LFBGA88 packages (x16 mode available) Description
Note: 1. In x8 mode A0 must be set to V IL. Otherwise, 00h will be output. 2. N/A = Not Applicable. Only the x16 mode is available with the LFBGA88 package.
Table 30. Block Status Register
Address bit0 1 (BA+2)h(1) 0 bit1 1 bit7-2 0 Last erase operation not ended successfully (2) Reserved for future features Block Protected Last erase operation ended successfully (2) Data 0 Selected Block Information Block Unprotected
Note: 1. BA specifies the block address location, A22-A17. 2. Not Supported.
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Table 31. Extended Query information
Address offset (P)h (P+1)h (P+2)h (P+3)h (P+4)h (P+5)h (P+6)h (P+7)h x16 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h x8(2) 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h Data (Hex) 50h 52h 49h 31h 31h CEh 06h 00h "P" "R" "I" Major version number Minor version number Optional Feature: (1=yes, 0=no) bit0, Chip Erase Supported (0=no) bit1, Suspend Erase Supported (1=yes) bit2, Suspend Program Supported (1=yes) bit3, Protect/Unprotect Supported (1=yes) bit4, Queue Erase Supported (0=no) bit5, Instant Individual Block locking (0=no) bit6, Protection bits supported (1=yes) bit7, Page Read supported (1=yes) bit8, Synchronous Read supported (0=no) bit9, Multi chip device (1=yes) bit10, Simultaneous operations supported (1=yes) Bits 11 to 31 reserved for future use Function allowed after Suspend: Program allowed after Erase Suspend (1=yes) Bits 1 to 7 reserved for future use Block Status Register bit0, Block Protect-Bit status active (1=yes) bit1, Block Lock-Down Bit status (not available) bits 2 to 15 reserved for future use VDD OPTIMUM Program/Erase voltage conditions VPP OPTIMUM Program/Erase voltage conditions OTP protection: No. of protection register fields Protection Register's start address, least significant bits Protection Register's start address, most significant bits n where 2n is number of factory reprogrammed bytes n where 2n is number of user programmable bytes Page Read: 2n Bytes (n = bits 0-7) Synchronous mode configuration fields Reserved for future use Query ASCII string - Extended Table Description
(P+8)h
0039h
72h
00h
(P+9)h (P+A)h (P+B)h (P+C)h (P+D)h (P+E)h (P+F)h (P+10)h (P+11)h (P+12)h (P+13)h (P+14)h (P+15)h
003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h
74h 76h 78h 7Ah 7Ch 7Eh 80h 82h 84h 86h 88h 8Ah 8Ch
01h 01h 00h 33h 00h 01h 80h 00h 03h 03h 03h 00h
Note: 1. Bit7 to bit4 are coded in Hexadecimal and scaled in Volt while bit3 to bit0 are in Binary Code Decimal and scaled in mV. 2. In x8 mode, A0 must be set to V IL, otherwise 00h will be output.
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APPENDIX C. FLOW CHARTS Figure 19. Write to Buffer and Program Flowchart and Pseudo Code
Start Write to Buffer E8h Command, Block Address
Note 1: Status Register must be read at the same address as the Write to Buffer command.
Read Status Register(1) NO b7 = 1 YES NO Write to Buffer Timeout YES
Note 2: N+1 is number of Words to be programmed
Write N(2), Block Address Try Again Later Write Buffer Data, Start Address
X=0
X=N NO Note 3: Next Program Address must have same A5-A21.
YES
Write Next Buffer Data, Next Program Address(3)
X=X+1
Program Buffer to Flash Confirm D0h
Read Status Register(1)
b7 = 1 YES Note 4: A full Status Register Check must be done to check the program operation's success. Full Status Register Check(4)
NO
End
AI07519
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Figure 20. Program Suspend & Resume Flowchart and Pseudo Code
Start Program/Erase Suspend Command: - write B0h to address PA
Write B0h Add PA(1)
Read Status Register(2)
do: - read status register
b7 = 1 YES b2 = 1 YES Write FFh
NO
while b7 = 1
NO
Program Complete
If b2 = 0, Program completed
Read Memory Array instruction: - write FFh - one or more data reads from other blocks
Read data from another block
Write D0h Add PA(3)
Write FFh
Program Erase Resume Command: - write D0h to address PA to resume erasure - if the program operation completed then this is not necessary. The device returns to Read Array as normal (as if the Program/Erase Suspend command was not issued).
Program Continues
Read Data
AI07514
Note: 1. PA = Program Address. The Program/ Erase Suspend command must be issued to the same address as the current Program command. 2. The Read Status Register command must be issued to the same address as the Program/ Erase Suspend command. 3. PA = Program Address. The Program/ Erase Resume command must be issued to the same address as the Program/ Erase Suspend command.
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Figure 21. Erase Flowchart and Pseudo Code
Start
Write 20h to Block Address
Write D0h to Block Address
Erase command: - write 20h to Block Address - write D0h to Block Address (A12-A17) (memory enters read Status Register after the Erase command)
Read Status Register(1)
NO Suspend
YES
do: - read status register - if Program/Erase Suspend command given execute suspend erase loop
b7 = 1
NO
Suspend Loop
while b7 = 1
YES b3 = 0 YES b4, b5 = 0 YES b5 = 0 YES b1 = 0 YES End
AI07515
NO
VPEN Invalid Error (2)
If b3 = 1, VPEN invalid error: - error handler
NO
Command Sequence Error
If b4, b5 = 1, Command Sequence error: - error handler
NO
Erase Error (2)
If b5 = 1, Erase error: - error handler
NO
Erase to Protected Block Error
If b1 = 1, Erase to Protected Block Error: - error handler
Note: 1. The Read Status Register command must be issued to the same address as the Block Erase command. 2. If an error is found, the Status Register must be cleared (Clear Status Register Command) before further Program or Erase operations.
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Figure 22. Erase Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h Add BA(1)
Program/Erase Suspend Command: - write B0h to BA
Read Status Register(2)
do: - read status register
b7 = 1 YES b6 = 1 YES Write FFh
NO
while b7 = 1
NO
Erase Complete
If b6 = 0, Erase completed
Read Memory Array command: - write FFh - one or more data reads from other blocks
Read data from another block or Program
Write D0h Add BA(3)
Write FFh
Erase Continues
Read Data
Program/Erase Resume command: - write D0h to BA to resume the Erase operation - if the Program operation completed then this is not necessary. The device returns to Read mode as normal (as if the Program/Erase suspend was not issued).
AI07516
Note: 1. The Program/ Erase Suspend command must be issued to the same address as the current Erase command. 2. The Read Status Register command must be issued to the same address as the Program/ Erase Suspend command. 3. The Program/ Erase Resume command must be issued to the same address as the Program/ Erase Suspend command.
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Figure 23. Block Protect Flowchart and Pseudo Code
Start
Write 60h Block Address
Block Protect Command - write 60h, Block Adress - write 01h, Block Adress
Write 01h Block Address
Read Status Register(1)
do: - read status register
b7 = 1
NO
while b7 = 1
YES YES VPEN Invalid Error
b3 = 1 NO
If b3 = 1, VPEN Invalid Error
YES b4, b5 = 1,1 NO YES b4 = 1 NO
Invalid Command Sequence Error
If b4 = 1, b5 = 1 Invalid Command Sequence Error
Block Protect Error
If b4 = 1, Block Protect Error
Write FFh
Read Memory Array Command: - write FFh
Block Protect Sucessful
AI07517b
Note: 1. The Read Status Register command must be issued to the same address as the Block Protect command.
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Figure 24. Blocks Unprotect Flowchart and Pseudo Code
Start
Set A23 Low (Add 000000h)
Blocks Unprotect Command - set Address 000000h (A23 Low)
Write 60h - write 60h - write D0h Write D0h
Read Status Register Set A23 High (Add 400000h) b7 = 1 NO
do: - read status register
while b7 = 1
YES YES VPEN Invalid Error
b3 = 1 NO
If b3 = 1, VPEN Invalid Error
YES b4, b5 = 1,1 NO YES b5 = 1 NO
Invalid Command Sequence Error
If b4 = 1, b5 = 1 Invalid Command Sequence Error
Blocks Unprotect Error
If b5 = 1, Blocks Unprotect Error
YES
A23 = Low? NO
If A23 = Low, - set Address 000000h (A23 Low) - repeat command
Write FFh
Read Memory Array Command: - write FFh
Blocks Unprotect Sucessful
AI07518b
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Figure 25. Protection Register Program Flowchart and Pseudo Code
Start
Write C0h
Write PR Add, PR Data(1)
Protection Register Program Command - write C0h - write Protection Register Address, Protection Register Data
Read Status Register(2)
do: - read status register
b7 = 1
NO
while b7 = 1
YES YES b3 = 1 NO YES b4 = 1 NO YES b1 = 1 NO VPEN Invalid Error If b3 = 1 VPEN Invalid Error
Protection Register Program Error
If b4 = 1 Protection Register Program Error
Protection Register Lock Error
If b1 = 1 Protection Register Lock Error
Write FFh
Read Memory Array Command: - write FFh
PR Program Sucessful
AI06159b
Note: 1. PR = Protection Register 2. The Read Status Register command must be issued to the same address as the Protection Register Program command.
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Figure 26. Command Interface and Program Erase Controller Flowchart (a)
WAIT FOR COMMAND WRITE
90h YES READ SIGNATURE
NO
98h YES CFI QUERY
NO
70h YES READ STATUS
NO
50h YES CLEAR STATUS
NO
READ ARRAY
E8h YES PROGRAM BUFFER LOAD
NO
20h(1) YES ERASE SET-UP
NO
FFh YES
NO
NO
D0h YES C A NO
PROGRAM COMMAND ERROR
D0h YES
ERASE COMMAND ERROR
B Note 1. The Erase command (20h) can only be issued if the flash is not already in Erase Suspend.
AI03618
Note: The commands must be issued to the addresses detailed in the Command Interface section, Table 5.
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Figure 27. Command Interface and Program Erase Controller Flowchart (b)
B A
ERASE
(READ STATUS)
READ STATUS
YES
Program/Erase Controller READY Status bit in the Status Register ? NO
READ ARRAY YES FFh NO
B0h YES
NO
READ STATUS ERASE SUSPEND
NO ERASE SUSPENDED YES
READY ? NO
WAIT FOR COMMAND WRITE
YES
READ STATUS
READ STATUS
YES
70h NO
READ SIGNATURE
YES
90h NO
CFI QUERY
YES
98h NO
PROGRAM BUFFER LOAD
YES
E8h
NO PROGRAM COMMAND ERROR NO D0h D0h NO READ ARRAY YES READ STATUS
(ERASE RESUME)
YES c
AI03619
Note: The commands must be issued to the addresses detailed in the Command Interface section, Table 5.
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Figure 28. Command Interface and Program Erase Controller Flowchart (c).
B C
PROGRAM
(READ STATUS)
READ STATUS READ ARRAY
YES
READY ? NO
Program/Erase Controller Status bit in the Status Register
B0h YES NO FFh PROGRAM SUSPEND NO PROGRAM SUSPENDED YES YES
NO
READ STATUS
READY ? NO
WAIT FOR COMMAND WRITE
YES
READ STATUS
READ STATUS
YES
70h NO
READ SIGNATURE
YES
90h NO
CFI QUERY
YES
98h NO
READ ARRAY
NO
D0h
YES
READ STATUS
(PROGRAM RESUME)
AI00618
Note: The commands must be issued to the addresses detailed in the Command Interface section, Table 5.
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REVISION HISTORY Table 32. Document Revision History
Date 10-Oct-2002 Version 1.0 First Issue Device code changed, LFBGA88 package added, Program /Erase Times and Program/Erase Endurance cycles table modified, Read Electronic Signature table modified, CFI Tables clarified in particular Table 31 and 29 (Extended Query Information and Device Geometry Definition). IOSC parameter added to Absolute Maximum Ratings table. IDD and VLKO clarified and IDDO and VPENH parameters added to DC Characteristics table. tPHWL parameter added to Reset, Power-Down and Power-Up AC Waveforms figure and Characteristics table. IDD1, IDD5, IDD2, IDD4, VIL, VIH and VLKO values refined in DC Characteristics table. Chip Enable state corrected for Power-Down in Table 4, Bus Operations. Addresses modified for Blocks Unprotect and Configure STS commands in Table 5, Commands. Addresses modified in Figure 24, Blocks Unprotect Flowchart and Pseudo Code. Figure 23, Block Protect Flowchart and Pseudo Code, clarified. Blocks Temporary Unprotect feature of Reset/Power Down pin no longer available. Program/Erase Suspend, Write to Buffer and Program, and Block Erase Commands clarified. Revision Details
11-Feb-2003
2.0
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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